Energy -Efficient CNNs Accelerator Implementation on FPGA with Optimized Storage and Dataflow

Convolutional neural networks (CNNs) has been widely used in computer vision and speech processing, and has achieved great success. However, the deployment of large-scale CNN model is limited by computing and memory in the smart embedded system. Through the current high parallel computing paradigm of CNNs accelerator, the computing requirements can be effectively met to achieve high throughput. However, because the communication cost may be higher than the computing cost for small smart platform, the energy consumption is still very high. In order to solve this problem, a new CNNs accelerator based on storage and data flow is proposed, which realizes energy-saving CNNs inference acceleration by minimizing data access and maximizing data reuse. This paper implements the accelerator on the Zynq UltraScale+MPSoC ZCU102 evaluation board, and evaluates the throughput and energy efficiency of the accelerator for typical vgg16 and tiny Yolo benchmark networks. Compared with other accelerators, the our accelerator improves the system energy efficiency by 6.3x, the system throughput by 41x, and the throughput of a single DSP by 7.63x.