A 2-Transistor-2-capacitor Ferroelectric Edge Compute-in-Memory Scheme with Disturb-Free Inference and High Endurance

This letter proposes C 2 FeRAM, a 2T2C/cell ferroelectric compute-in-memory (CiM) scheme for energy-efficient and high-reliability edge inference and transfer learning. With certain area overhead, C 2 FeRAM achieves the following highlights: (i) compared with FeFET/FeMFET, it achieves disturb-free CiM and much higher write endurance (equal to FeRAM), leading to $100\times $ inference time with < 1% accuracy drop for VGG8 in CIFAR-10 dataset, along with the enhanced endurance for weight updates, e.g., CiM-based transfer learning; (ii) compared with 1T1C FeRAM inference cache, the achieved disturb-free feature and CiM capability in C 2 FeRAM lead to improvements of $4\times $ energy, $200\times $ speed, and 3.2e $5\times $ life cycles. Such benefits highlight an intriguing solution for future intelligent edge AI.