MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks

This article presents multistep accumulation capacitor coupling static random-access memory (MACC-SRAM), capacitor-based in-memory computing (IMC) SRAM macro for 4-b deep convolutional neural network (DNN) inference. The macro can simultaneously activate all its 128 $\times$ 128 custom 9T1C bitcells to perform the vector–matrix multiplication (VMM). MACC-SRAM also integrates 128 stepwise-charging and discharging input drivers (SCD-IDRs) to efficiently convert the digital codes of the input activations into analog voltages in a 2-b serial fashion. As a result, it can save up to 66% of the capacitor-driving energy. Also, the macro adopts an adder-first architecture to reduce the analog-to-digital (A/D) conversion overhead for the analog-mixed-signal (AMS) computation. The partial sums of the four adjacent rows, representing different bit positions in the 4-b weights, are first accumulated with an analog switched-capacitor adder and then converted to digital codes by a 6-bit successive approximation register (SAR) analog-to-digital converter (ADC). Compared with the ADC-first architecture, where partial sums of each row are first converted to digital codes and then accumulated in the digital domain, the adder-first architecture can save 60.7% of the area and 66.7% of the energy consumption of the A/D conversion. Moreover, the co-optimization of the DNN model by increasing the sparsity further reduces 39.4% of the capacitor-driving energy with a neglectable 0.4% DNN accuracy loss. We prototyped the macro in 28 nm technology, and the measurement shows an energy efficiency of 163 tera-operations per second per watt (TOPS/W) and a throughput of 211 giga-operations per second (GOPS) for a 4-b/4-b DNN model under 0.9 V supply, among the highest of the recent IMC SRAMs.