Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation

Temperature affects performance, power, and en-ergy efficiency in modern system-on-chip (SOC) applications. Transport properties of nanoscale devices are fundamentally different from those predicted using conventional long-channel device transport models. In this work, a Monte Carlo (MC) calibrated model based on nanosheet FETs, geared towards AIO technology node, is used to study thermal effects on Power, Performance, Area (PPA) metrics at IP block-level. Given the packaging and the cooling configuration, SOC operational junction temperature (Tj) depends on the power it dissipates. At the same time, the dissipated power itself varies with temperature, with the dynamic and the leakage power components tending to show weak and strong sensitivity respectively. A look-up table (LUT) based electro-thermal model is proposed to account for this power-temperature interdependency at IP block-level with the capability of tracking localized hotspots with desired accuracy and run-time efficiency trade-offs. The resulting self-consistent solution can prove to be effective in assessing system-level cooling requirements early in the product development phase.