Mismatch Calibration Strategy for Query-Driven AER Read-out in a Memristor-Cmos Neuromorphic Chip

The emergence of hybrid memristor-CMOS technologies open a promising way to implement compact neuromorphic systems with dense layers of neurons interconnected through memristive synapses for high-speed and low-power inference applications and online learning. However, there are still many practical issues which should be overcome, especially related to the memristive devices, but also to the CMOS circuitry. In particular, transistor mismatch can produce very different behaviors between neurons, reducing dramatically the performance of the system. In this work, we propose a mismatch calibration strategy to compensate this effect by performing a post-fabrication characterization of neurons behavior and applying proportional threshold voltages at the comparator which activates the generation of output events. We have implemented the proposed strategy on a CMOL-like memristor-CMOS neuromorphic chip with 64 input neurons, 64 output neurons and 4096 1T1R synapses, fabricated in 130nm CMOS with 200nmsized Ti/HfOx/TiN memristors on top, obtaining a performance improvement from 49% to 80% in an inference experiment.