Low-frequency Noise in the Double SOI (DSOI) MOSFETs with Back-Gate Control

In this paper, the impact of the back-gate voltage (Vb) on the low-frequency (1/f) noise is evaluated for the 180 nm double silicon-on-insulator (DSOI) NMOS, fabricated with various thicknesses of first buried oxide (BOX1) layer (145/50 nm). Both positive and negative V b increased the measured normalized drain current power spectral density (PSD) for more than ten-fold in DSOI standard devices with 145 nm BOX1, while the normalized PSD decreases with V b going up in devices with 50 nm BOX1. By comparing with CNF+CMF model, interface trap density and the Coulomb scattering coefficient are extracted with the back-gate voltage applied. The interface trap density increases in standard devices for both positive and negative V b , but decreases with increasing back-gate biasing from - 10 V to 10 V in devices with 50 nm BOX1. The interface trap density shows a similar back-gate coupling effect with threshold voltage under the influence of different thickness of BOX1. The CNF and CMF noise variation under back-gate voltage can be explained by the significant fluctuation in drain current.