Managing Crosstalk in Multi-GHz Front Side Clock for Back Side Power Enabled Sub-2nm 2D/3D ICs

This paper addresses several aspects of clock net distribution in the context of sub-2nm CMOS ICs, where power delivery networks have been enabled to move to the back side of the chip (BSPDN). Moving the mainstream power delivery network to the back side significantly reduces the self-capacitance of the top back-end-of-line (BEOL) metal layers (Mz). This benefits the clock energy consumption (reduced down to 10% of FSPDN+FS-Mz clock). However, clock nets routed on Mz layer with no power supply around, make the clock very noisy. In this paper, we show that in case of BSPDN, a set of correlated aggressors, can couple to the clock signal and contribute a data-dependent jitter of up to 40% of the clock period, due to an unshielded or poorly shielded clock. We also show that due to undefined return paths, the self and mutual inductive noise can be a potential cross talk mechanism degrading the clock quality further, even with a shielded clock in place. This gets worse for 3D integration specially in F2F (Face to Face) bonding option. We also propose that moving a majority of clock to the back side along with the BSPDN, can be a better alternative than only providing shielding on the front side. Energy consumed in BSPDN+BS-Mz is just ~15% of the energy compared to FSPDN+FS-Mz clock and a much improved signal integrity.